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Non-photonic, Lightspeed Adder
AMD Product Improvement Idea
Submitted 1 year ago
Using Complementary Pass Logic (CPL) design rules, assuming a 45nm Source-to-Drain distance (old) and ε_r = 3.9 for silicon dioxide, then signals can travel at ~1.5e8m/s (=c/SQRT(ε_r * µ_r) across the 45nm Source-to-Drain distance, and a single-bit Add (new design) with 0.3femtosecond Carry information, therefore a 64-bit wide Add in ~20femtoseconds. Is NOT a CLA Adder.
As a simpler example, can make an CPL (A.XOR.B = F) that usually consists of Inverter, AND, and OR, thus 3 Gate delays of ~20ps each which with CPL logic reduces to 0.3femtoseconds. An assumption is taken that A asserts before B, a given since the data bus cannot move A and B simultaneously.
There is also a way to reduce Gate delay into the femtoseconds, without need for resistive Gate damping that causes the RC time delay of 20ps.
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